AM3352BZCZA100
Features
Usque ad 1-GHz Sitara™ ARM® Cortex®
-A8 32‑Bit RISC Processor
- NEON™ SIMD Coprocessor
– 32KB of L1 Instructiones et 32KB datae Cache cum uno errore
Deprehensio
- 256KB of L2 Cache Cum Error Correctionis Code (ECC)
– 176KB of On-Chip Boot ROM
- 64KB of Dedicavit RAM
- Emulation et Debug - JTAG
- Interpellare Controller (usque ad CXXVIII interrumpere supplicum libellis)
On-Chip Memoria (Shared L3 RAM)
- 64KB of General-Propositum On-Chip Memoria Controller (OCMC) RAM
- Ad omnes Masters promptu
- Sustinet retentione pro Fast Wakeup
Memoria externa interfaces (EMIF)
– mDDR(LPDDR), DDR2, DDR3, DDR3L
Controller
- mDDR: 200-MHz Horologium (CD-MHz Data Rate)
- DDR2: 266-MHz Horologium (532-MHz Data Rate)
- DDR3: 400-MHz Horologium (DCCC-MHz Data Rate)
- DDR3L: 400-MHz Horologium (DCCC-MHz Data Rate)
- 16-bit Data Bus
- 1GB totius Addressable Space
- subsidia una x16 vel duae x8 Memoria Fabrica configurationis
- General-Propositum Memoria Controller (GPMC)
- Flexibile 8-bit et 16-bit Asynchronae Memoriae instrumenti usque ad Septem Drachmas Selecta (NAND, NOR, Muxed-NOR, SRAM)
- Usus BCH Code ut suscipe 4-, 8-, vel 16-bit ECC
- Usus Hamming Code ut suscipe I-bit ECC
- Error Locator OMNIBUS (ELM)
- Usus in Conjunctione Cum GPMC ad Locare Inscriptiones Datae Errorum Syndrome Polynomiales Generatae Utens BCH Algorithmo
- subsidia 4-, 8- et XVI-bit per DXII-Byte Clausus Error Location Ex BCH Algorithms
Programmable Real-time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
- Protocolla subsidia qualia sunt EtherCAT®, PROFIBUS, PROFINET, AETHERE/IP™, et MORE.
- Duo Programmable Real-time Unitates (PRUs)
- 32-bit Load/Store RISC Processor Capable of Running at 200 MHz
- 8kb Instructionis ram Cum Single-Error Deprehensio (par)
- 8KB of Data Ram Cum Single-Error Deprehensio (paritas)
- Single Cycle XXXII-bit Multiplier Cum LXIV-bit Accumulator
- Consectetur GPIO amet praebet ShiftIn / de Support et parallela Claustrum in externi signum
- 12KB of Ram Shared Cum Single-Error Deprehensio (paritas)
- Tres 120-Byte Register Banks promptu per singulos PRU
- Interpellare Controller (INTC) pro tractantem ratio potenti Events
- Loci Interconnect Bus pro Dominis internis et externis connectere ad Resources intra PRU-ICSS
- Peripherales Intus PRU-ICSS:
- Una UART Portus Cum Fluunt Imperium acus,
Sustinet ad XII Mbps
- One Consectetur Captura (eCAP) OMNIBUS
- Duo MII Aer portus qui Support Industrial
Aer, ut EtherCAT
- One MDIO Port
Potentia, Reset et Horologium Management (PRCM) Module
- Controls ingressu et Exitu sta-By et profundus-Somnus Modi
-- Responsible for Somnus Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
- Horologiorum
- Integrated 15- ad XXXV-MHz summus Frequency
Oscillator generare solebat horologium Reference pro variis systematibus et horologiis periphericis
- subsidia singula Horologium activare et inactivare
Imperium pro Subsystems et Peripherales to
Faciliorem reducta Power consummatio
- Quinque ADPLLs ad Generare Ratio Horologiorum
(MPU Subsystem, DDR Interface, USB et Peripherales [MMC et SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Horologium)
