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DSPIC30F5011-30I/PT

Description:

• Modified architecturae Harvardianae
• C compilator optimized institutionis architecturae
• modos addressing flexibilia
• 83 base instructions
• 24-bit instructiones latae, datae 16-bitae semitae
• 66 Kbytes in-chip Mico programma spatii


Product Detail

Product Tags

FeaturesHigh-Performance Modified RISC CPU

1.Modified Harvard architectura
2.C compilator optimized institutionis architecturae
3.Flexible addressing modos
4.83 basis instructiones
5.24-bit instructiones latae, datae 16-bitae semitae
6.66 Kbytes on-chip Flash program space
7.4 Kbytes de in-chip data RAM
8.1 Kbyte de notitia nonvolatili EEPROM
9.16 x 16-bit opus mandare ordinata
10.Up ad XXX MIPS operationem:
- DC ad 40 MHz horologium externum input
- 4 MHz-10 MHz oscillator input cum
PLL activa (4x, 8x, 16x);

Ad XLI fontes adjicias

- Octo user selectable prioritas gradus
- Quinque externa fontes interpellare
- Quattuor processus laqueos

DSP Features

1.Dual data arcessere
2.Modulo et Bit-reverso modos
3.Two XL-aliquantulus accumulatores ad libitum
satietatem logica
4.17-bit x 17-bit Unius cycli hardware fractus/.
Integer multiplicator
5.All DSP instructiones sunt unius exolvuntur
- Multiplica-accumulate (MAC) operandi
6.Single exolvuntur ± XVI trabea

Features periphericis

1.High-current sink/source I/O paxillos: 25 mA/25 mA
2.Five 16-bit timers/calculis;optionally par up
XVI frenum timers in XXXII frenum timor modulorum
3.16 frenum Capere input functiones
4.16-bit Compare/PWM output functions
5.Data converter interface (DCI) subsidia communia
protocolla audio codec, inter I2S et AC'97 .
6.3-filum SPI modulorum (sustinet quattuor Frame modos)
Moduli sustinet 7.I2C™ Multi-Magistri/servi modum
ac VII-bit / X-bit addressing
8.Two modules addressable UART cum FIFO buffers
9.Two can bus modulorum obsequentem Can 2.0B vexillum

Analog Features

1.12-bit Analog-ad-Digital Converter (ADC) with:
- 200 ksps conversion rate
- Ad XVI initus channels
- Conversio available in Somno et Otioso
2.Programmable Low-Voltage Detection (PLVD)
3.Programmable Brown-e Deprehensio et Reddere generationem
Speciali Microcontroller Features:
4.Enhanced Mico memoria progressio:
- 10,000 extermina / scribe cyclum (min.) pro industriae temperatura range, 100K (typica)
5.Data EEPROM memoria;
- 100,000 extermina / scribe cyclum (min.) pro temperatura industriae range, 1M (typica)
6.Self-reprogrammable sub software imperium
7.Power-on Reddere (POR), Power-sursum Vicis (PWRT) et Oscillator Satus-up Vicis (OST)
8.Flexible Watchdog Timer (WDT) cum in-chip low- potentia RC oscillator ad certa operatio
9.Fail-tutus Horologium Monitor operatio:
- Detegit horologium defectum et virgas in chip humilis potentia RC oscillatoris
Codicis programmabilis praesidio:
10.In-Circuit Serial Programming™ (ICSP™) programmandi facultatem
11.Selectable Power Management modos:
- Somnus, Otiosus et Alternis Horologii modos
CMOS Technology:
12.Low-virtus, summus velocitas technologiae Flash
13. Wide operans voltage range (2.5V ad 5.5V)
14.Industrial et extensa temperatus regionesve delata
15.Low potentia consummatio


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